SK AHMED PASHA, D. SUMALATHA, A. VENU GOPAL. High-Performance Vedic Multiplier with Modified HSCG-SCG Adder for Low-Power and High-Speed Arithmetic Processing . Journal of Computational Analysis and Applications (JoCAAA), [S. l.], v. 31, n. 1, p. 248–256, 2023. Disponível em: https://www.eudoxuspress.com/index.php/pub/article/view/2046. Acesso em: 11 aug. 2026.