Scaling Gate-All-Around (GAA) Transistor Architectures for Sub-2nm AI  Accelerators Using Atomically Thin 2D Materials

Pawan Kumar Singh

Scaling Gate-All-Around (GAA) Transistor Architectures for Sub-2nm AI Accelerators Using Atomically Thin 2D Materials

Authors

Pawan Kumar Singh

Keywords:

Gate-all-around transistor, 2D materials, sub-2nm technology, AI accelerator, nanosheet, semiconductor scaling

Abstract

The relentless pace of AI workloads has pushed semiconductor manufacturers to the physicallimits of silicon scaling. Gate-all-around (GAA) transistor architectures have replaced FinFETsat the leading nodes because they offer superior electrostatic control at ultra-short channel lengths, but as the industry moves toward the 2 nm node and beyond, even nanosheet GAAdevices built from silicon face fundamental limits.

References

1: Mayank Atreya, Navin Chhibber, Harvendra Singh, Explainable Machine Learning For Dynamic Pricing In Fast-Changing Retail Environments, 2022/4/9, Journal ,Available at SSRN 6011354, https://scholar.google.com/citations?view_op=view_citation&hl=en&user=fyViF1UAAAAJ&citation

_for_view=fyViF1UAAAAJ:LkGwnXOMwfcC.

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Published

2024-11-20

How to Cite

Pawan Kumar Singh. (2024). Scaling Gate-All-Around (GAA) Transistor Architectures for Sub-2nm AI Accelerators Using Atomically Thin 2D Materials . Journal of Computational Analysis and Applications (JoCAAA), 33(08), 9338–9350. Retrieved from https://www.eudoxuspress.com/index.php/pub/article/view/5713