Design And Implementation of Low Power MAC Unit for DSP Applications
Keywords:
Multiply-Accumulate (MAC) unit, Vedic Multiplier, VLSI Design, Low-Power Design, RTL to GDSII, Physical Synthesis, Wallace Tree, Pipelining.Abstract
The Multiply-Accumulate (MAC) unit is a critical arithmetic block in Digital Signal Processing(DSP) and neural network accelerators. This paper presents the design, synthesis, and physical implementation of a high-performance
References
Kavindra Dwivedi, R.K. Sharma Sharma, Ajay Chunduri, "Hybrid Multiplier Based Optimized MAC Unit", 2018 9th International Conference on Computing Communication and Networking Technologies (ICCCNT), pp. 1-4, 2018.
Basavoju Harish, M.S.S.Rukmini, K.Sivani Design of MAC unit for digital filters in signal processing and communication , International Journal of Speech technology , 25 561-565(2022), March 2021
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Published
2025-08-20
How to Cite
Sushma, Dr. Mahesh B Neelagar. (2025). Design And Implementation of Low Power MAC Unit for DSP Applications . Journal of Computational Analysis and Applications (JoCAAA), 34(8), 434–442. Retrieved from https://www.eudoxuspress.com/index.php/pub/article/view/3717
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