Design and Implementation of 12-bit SAR ADC with Nanometer  Technology

Nagaraja H, Dr H C Hadimani

Design and Implementation of 12-bit SAR ADC with Nanometer Technology

Authors

Nagaraja H, Dr H C Hadimani

Keywords:

12-bit SAR, 45nm Technology, Functional Verification, Synthesis and Physical synthesis, Optimization

Abstract

This work presents the design, synthesis, and physical implementation of a 12-bit SuccessiveApproximation Register (SAR) Analog-to-Digital Converter (ADC) optimized for nanometerscale CMOS technology. The architecture integrates a compact digital control unit, comparatorinterface, and DAC logic

References

Razavi, B. Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2001.

Johns, D. A., & Martin, K. Analog Integrated Circuit Design. Wiley, 1997.

Maloberti, F. Data Converters. Springer, 2007

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Published

2025-03-20

How to Cite

Nagaraja H, Dr H C Hadimani. (2025). Design and Implementation of 12-bit SAR ADC with Nanometer Technology . Journal of Computational Analysis and Applications (JoCAAA), 34(8), 11–18. Retrieved from https://www.eudoxuspress.com/index.php/pub/article/view/3443