EMPOWERING ULTRA LOW POWER WITH RISC – V ISA EXTENSION USING REVERSIBLE LOGIC  GATES FOR IOT DEVICES

Dr.S.JAGADEESH, DODDA AKSHARA , ANANTHARAM SAI SREEJA, JANUPALA AKSHAYA

EMPOWERING ULTRA LOW POWER WITH RISC – V ISA EXTENSION USING REVERSIBLE LOGIC GATES FOR IOT DEVICES

Authors

Dr.S.JAGADEESH, DODDA AKSHARA , ANANTHARAM SAI SREEJA, JANUPALA AKSHAYA

Keywords:

Reversible Logic Gates, RISC-V, Ultra-Low Power, IoT Devices, Energy Efficiency, Multipliers, Arithmetic Units, Instruction Set Architecture.

Abstract

The rapid proliferation of Internet ofThings (IoT) devices has underscoredthe necessity for processors thatprioritize energy efficiency withoutcompromising performance.Traditional processors, often based onirreversible logic gates, inherentlydissipate energy due to information

References

Chiwande, S. S., & Dakhole, P. K. (2020). Ultra Efficient Reversible Logic Multiplier Design. International Journal of Intelligent Systems and Applications in Engineering.

Kambhampati, S. B., et al. (2020). Implementation of Reversible Logic Gates for 8-Bit Multiplier. International Journal of Engineering Research & Technology.

Downloads

Published

2024-03-13

How to Cite

Dr.S.JAGADEESH, DODDA AKSHARA , ANANTHARAM SAI SREEJA, JANUPALA AKSHAYA. (2024). EMPOWERING ULTRA LOW POWER WITH RISC – V ISA EXTENSION USING REVERSIBLE LOGIC GATES FOR IOT DEVICES . Journal of Computational Analysis and Applications (JoCAAA), 33(2), 1385–1392. Retrieved from https://www.eudoxuspress.com/index.php/pub/article/view/2540