Power-Aware VLSI Design Using Multi-Threshold CMOS Technology
Keywords:
CMOS, Low Power, Voltage, VLSI, multiplexer & Decoder, Low Control DesignAbstract
in CMOS rationale circuits, the decrease in the threshold voltage because of voltagescaling prompts increment in the sub limit spillage current and henceforth static power dispersal.In spite of the fact that power utilization is critical for current VLSI outline, operation speed andpossessed territory are as yet the principle necessities of the VLSI plan
References
. P. Verma, R. A. Mishra, “Leakage power and delay analysis of LECTOR based CMOS circuits”, Int’l conf. on computer & communication technology ICCCT 2023.
. H. Narender and R. Nagarajan, “LECTOR: A technique for leakage reduction in CMOS circuits”, IEEE trans. on VLSI systems, vol. 12, no. 2, Feb. 2021.
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Published
2024-12-25
How to Cite
Mrs.S.Kanimozhi,Dr.J.Amutha,Mr.P.Sudarsan,Mrs.B.Sugnaya. (2024). Power-Aware VLSI Design Using Multi-Threshold CMOS Technology . Journal of Computational Analysis and Applications (JoCAAA), 33(05), 1311–1317. Retrieved from https://www.eudoxuspress.com/index.php/pub/article/view/2530
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