OPTIMIZING MULTIPLIER: A GLOBAL APPROACH FOR FPGA DESIGN

Authors

  • Dr.SIVANAGI REDDY KALLI, ARAKALA SRIDEVI, ANUMALLA SRISINDHU, HANUMANDLA HARSHINI

Keywords:

FPGA, multiplier optimization, digital signal processing, machine learning, power efficiency

Abstract

Field-Programmable Gate Arrays(FPGAs) have become integral in highperformance computing applications,particularly in digital signal processing(DSP) and machine learning tasks,where efficient multiplication is crucial.Traditional multiplier designs oftenface challenges

References

Parhami, B. (2010). Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press.

Chandrakasan, A., Brodersen, R. (1995). Low Power Digital CMOS Design. Kluwer Academic Publishers.

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Published

2024-04-16

How to Cite

Dr.SIVANAGI REDDY KALLI, ARAKALA SRIDEVI, ANUMALLA SRISINDHU, HANUMANDLA HARSHINI. (2024). OPTIMIZING MULTIPLIER: A GLOBAL APPROACH FOR FPGA DESIGN. Journal of Computational Analysis and Applications (JoCAAA), 33(4), 800–808. Retrieved from https://www.eudoxuspress.com/index.php/pub/article/view/2501

Issue

Vol. 33 No. 4 (2024): Selected Papers on Computational Techniques Across Multidisciplinary Fields: Innovations and Applications

Section

Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.